In order to meet the increasing needs for more I/O pins with narrower pitches in the field of semiconductor packages, a technique called "stud bump method" is known. This is a method of forming an electrode on semiconductor chips. This technique is specifically disclosed in the Japanese Laid-open Patent No. 63-304587 (1988). A summary thereof is described below.
FIGS. 18(a) through 18(d) are process sectional views for explaining the bump electrode forming process of the prior art.
As shown in FIG. 18(a), a ball 3 is formed by an electric torch on the tip of the wire 2 drawn out from the tip of a bonding capillary 1. As shown in FIG. 18(b), the ball 3 is bonded to an electrode pad 5 on an LSI chip substrate 4 by the capillary 1, and a base part 6 is formed. In succession, as shown in FIG. 18(c) and FIG. 18(d), the wire connected to the base is passed into the hole of the capillary, the capillary is moved in a loop form, and a protrusion is formed with folded wire 2 on the base part 6. By subsequent cutting of the wire, a bump electrode is completed.
FIG. 19 is a sectional view of a bump electrode formed by this method. Since the top surface of the base 6 is flat, the force to retain the tail of the bonded wire 2 is insufficient, and due to the movement of the capillary (when cutting off the wire after bonding the tail), the tail of the wire is often dislocated from the base 6. As a result, the shape of the obtained bump electrode is not as specified. Because reformation of the electrode is practically impossible, LSI chips having such a bump electrode must be discarded as defective products.